A dynamic random-access memory (DRAM), is typically constructed of memory cells comprising one transistor and one capacitor. A larger capacity memory thus can be realized when the memory cell area is reduced in size. Because the storage of data is accomplished by holding a charge on the capacitor, there is the problem that, with the passage of time, the charge held in the capacitor discharges, and the storage data is lost. In order to accurately save the stored data, a DRAM typically includes the so-called refresh operation. The refresh operation performs a rewrite of the data for the memory cells at a fixed time spacing. A self-refresh circuit is typically provided in the ordinary DRAM to control the refresh operation.
FIG. 5 is a schematic showing one construction example of a self-refresh circuit. The self-refresh circuit shown in the figure is constructed by means of the self-refresh oscillator 10, the counter 20, the interval time detector 30, the entry time detector 40, the mode set/reset control circuit 50, the internal RAS control circuit 60, and the internal RAS generator circuit 70.
The self-refresh circuit is started by means of a control signal CBR. The counter 20 starts the count in response to a clock signal CLK sent from the self-refresh oscillator 10, and the count value CNT is output to the interval time detector 30 and the entry time detector 40.
A value corresponding to the desired interval time is set in the interval time detector 30, and a value corresponding to the desired entry time is set in the entry time detector 40, respectively. If the value set as the entry time and the counter value CNT match in the entry time detector 40, a mode set signal MST is output, the refresh mode is set by means of a mode set/reset control signal 50 in response to this, and the mode signal MDST is switched, for example, from a low level to a high level.
By this means, the pulse signal INTRAS for the purpose of the internal refresh is generated by means of the internal RAS generator circuit 70, and output. At the same time, the counter 20 is reset by means of the internal RAS control signal circuit 60, and the count is newly begun. When the count value CNT and a value that was set beforehand in the interval time detector 30 match, the control signal IST is output from the interval time detector 30, and in response to this a pulse signal INTRAS is newly sent by means of the internal RAS generator circuit 70. Then, the counter 20 is again reset by means of the internal RAS control circuit 60, and the count is begun. This operation is repeatedly conducted until the control signal CBR is reset, the pulse signal INTRAS is generated by means of the self-refresh circuit, and the refresh of the DRAM is conducted in response to this.
FIG. 6 is a waveform chart showing the operation of the self-refresh circuit. As is illustrated, when the control signal CBR is placed in the active state, for example, in the state of a high level, the self-refresh circuit is started. The counter 20 is started by means of the internal RAS control circuit 60, and the counter operation by means of the counter 20 is initiated. Also, as for the self-refresh oscillator 10, when the control signal CBR is set to the high level, its oscillation operation is reset by means of the internal RAS control circuit 60.
The count value from the counter 20 and the preset value are compared by means of the entry time detector 40, and if matching, the mode control signal MST is generated, and is output to the mode set/reset control circuit 50. In response to this, the mode signal MDST is switched from the low level to the high level by means of the mode set/reset control circuit 50, and the refresh mode is set. The time T.sub.E from when the control signal CBR is set to the active state until the mode signal MDST is switched to the high level is the entry time, and is controlled by means of the entry time detector 40.
When it is set to the refresh mode, the first pulse signal INTRAS is generated by means of the internal RAS generator circuit 70 and is output, the counter 20 is reset in response to this, and a new count is begun. When the count value CNT matches the value set beforehand in the interval time detector circuit 30, the control signal IST is output by means of the interval time detector 30, and the second pulse signal INTRAS is generated by means of the internal RAS generator circuit 70 in response to this. The counter 20 is again reset in response to this pulse signal INTRAS, and the count is begun.
The spacing T.sub.R for the second and the first pulse signals INTRAS is controlled by means of the interval time detector 30. Also, the width T.sub.D for the pulse signal INTRAS is controlled, for example, by means of the delayed time of the delay circuit provided in the internal RAS generator circuit 70. In the case of a 64 Mb DRAM, the spacing T.sub.R for the pulse signal INTRAS is set, for example, to 16 .mu.s, and the pulse with T.sub.D of the pulse signal INTRAS, for example, is set to 50-60 ns.
The above-mentioned operation is repeatedly conducted, and the pulse signal INTRAS is repeatedly generated for the cycle T.sub.R until the control signal CBR is reset to the low level. The time from when the control signal CBR is set, and the initial pulse signals INTRAS is generated, until the final pulse signal INTRAS is ended, is one cycle of the refresh operations. For example, in the case of a 64 Mb DRAM, all of the memory cells are refreshed by means of the pulse signal INTRAS being generated 4096 times. As mentioned above, in the event the cycle T.sub.R for the pulse signal INTRAS is 16 .mu.s, one cycle for the refresh becomes (16 .mu.s.times.4096 =65.5 ms).
The self-refresh oscillator 10, for example, is constructed by means of a ring oscillator constructed by means of connecting an odd number of stages of inverters in a ring configuration and a current source that supplies current to the oscillator. One construction example of the current supply circuit is shown in FIG. 7. FIG. 7(a) is a schematic of the current source circuit 100, and FIG. 7(b) shows its equivalent circuit.
As is shown in FIG. 7(a), the current source circuit 100 is constructed by means of the pMOS transistors PT1, PT2, PT3, PT4, PT5, PT6, switches SW1, SW2, SW3, SW4, SW5, and the nMOS transistor NT1.
The pMOS transistors PT1 to PT6 are connected in series between the power supply voltage VDL and the node ND1. The gates of these pMOS transistors are connected to the common potential V.sub.ss, and their base regions back gates are connected in common to the power supply voltage VDL. Also, the switches SW1, SW2, SW3, SW4, SW5 are respectively connected between the source and drain of the pMOS transistors PT2, PT3, PT4, PT5, PT6.
The switches SW1 to SW 5, for example, are constructed by means of metal switches.
Since the pMOS transistors PT1 to PT6 are constructed by linear type regions, the partial circuits constructed by means of these transistors can be considered as being replaced by resistive elements R having prescribed resistance values. By this means, the current source circuit 100 can be simplified by means of the equivalent circuit shown in FIG. 7(b). In other words, the current source circuit 100 can be shown by means of the resistive element R that is connected between the power supply voltage VDL and the node ND1, and the nMOS transistor NT1 that is diode connected. The gate and drain of the nMOS transistor NT1 are connected in common to the node ND1, and the source is connected to the common potential V.sub.ss. The bias voltage V.sub.BIAS is output by means of the node ND1. Also, the node ND1 is connected to the gate of each nMOS transistor that supplies current to the inverter that constructs the oscillator, and a current mirror current source is constructed by means of these MOS transistors and the nMOS transistor NT1.
Here, by means of regulating the ON/OFF state of the switches SW1 to SW5, the resistance values of the equivalent resistive elements R of the pMOS transistors PT1 to PT6 are controlled, and the current value supplied to the oscillator the current mirror circuit in it is controlled in response to this. The oscillating frequency of the oscillator is controlled by means of the current value supplied. When the supplied current is large the oscillator frequency is controlled to be high, and conversely, when the supplied current is small the oscillator frequency is controlled to be low.
In other words, the frequency of the clock signal CLK generated by means of the oscillator is controlled in response to the amount of current supplied to the oscillator. Since the self-refresh circuit conducts a count of the counter 20 in response to the clock signal CLK from the self-refresh oscillator 10, and generates the pulse signal INTRAS, the frequency of the pulse signal INTRAS for the purpose of the refresh is controlled in response to the frequency of the clock signal CLK generated by means of the self-refresh oscillator 10.
In the above-mentioned oscillator circuit used in the past, the current value supplied from the current source circuit changes due to the temperature characteristics of the MOS transistors, and there is the disadvantage that the frequency of the clock signal CLK generated in response to that will fluctuate.
For example, there is a tendency for the threshold voltage V.sub.th of the MOS transistors to drop accompanying a temperature rise, and the drain current of the MOS transistor has a negative temperature characteristic temperature-dependent characteristic. Because of this, in the current source circuit, the current supplied to the node ND1 through the medium of the pMOS transistors drops due to a temperature rise, and since, as a result, the current value supplied to the oscillator drops during high temperatures, it has a characteristic in which the frequency of the clock signal CLK drops accompanying a temperature rise, which is the so-called negative temperature coefficient.
On the other hand, in the memory cell of the DRAM, the leakage current of the memory cell increases accompanying a temperature rise, and the data holding characteristics of the memory cell worsens. In order to accurately hold the storage data, it is necessary to make the refresh operating cycle short during high temperatures, in other words, to set the refresh operating frequency high.
FIG. 8 shows the changes of the leakage current of the memory cell and the changes of the refresh frequency in response to temperature changes. In FIG. 8, A shows the changes of the leakage current of the transistor in response to the temperature changes, B shows the changes of the refresh cycle necessary in order to accurately maintain the storage data of the memory device, based on the changes in the leakage current, and C shows the actual changes of the refresh frequency undergoing the influence of temperature changes.
As is illustrated, the semiconductor memory device, for example, is assumed to operate in the temperature range of from temperature T.sub.1 to T.sub.2. At the high temperature side of T.sub.2 the leakage current is large, and the necessary refresh frequency is set to f.sub.2 based on that. On the other hand, at the low temperature side of T.sub.1, since the leakage current is reduced, the necessary refresh frequency is f.sub.1. However, as is illustrated, since the oscillator frequency of the oscillator circuit rises during a low temperature, the actually obtained refresh frequency becomes f.sub.3. In other words, due to the fact that the refresh is conducted more than necessary during a low temperature, needless electrical power is consumed.
In this way, in the ordinary DRAM, since the frequency for the refresh operation is set to match the data holding characteristics of the memory cell during high temperature, at low temperature, since the data holding characteristics of the memory cell become good, this means that the refresh is needlessly conducted during low temperature. In the DRAM, the change to a low power consumption for the self-refresh mode is an important problem. In order to suppress the power consumption as much as is possible, it is essential that the frequency of the refresh operations be optimized in response to the ambient temperature. At that time, the temperature characteristics of the self-refresh oscillator 10 become a hindrance to the optimization.
This invention was made looking back at this type of information, and its purpose is to offer an oscillator circuit that can realize an oscillator circuit in which the oscillating frequency is set high during high temperature and in which the oscillating frequency is set low during low temperature, that can optimize the refresh operating frequency in response to this, and which can suppress needless power consumption.